//////////////////////////////////////////////////////////////////////////////////
// Company:        RIT
// Engineer:       Cody Cziesler and Nick Desaulniers
//
// Create Date:    3:03 04/17/2011
// Design Name:    reg_block
// Module Name:    reg_block
// Project Name:   Omicron
// Target Devices: Xilinx Spartan-3E
// Tool versions:
// Description:    The register block for the instruction decode
//
// Revision 0.01 - File Created, Tested, Works great (CRC)
// Revision 1.00 - Changed the number of registers, untested (CRC)
// Revision 2.00 - Changed size of raddr1, raddr2, waddr (CRC)
// Revision 3.00 - Added check for register $0 (CRC)
// Revision 4.00 - Spacing, fixed register $0 (CRC)
// Revision 5.00 - Changed registers to have individual reg's (CRC)
// Revision 6.00 - Removed combinational loop (CRC)
// Revision 7.00 - Really removed combinational loop on rdata1/rdata2 (CRC)
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

`include "include.v"

module reg_block(
  input [2:0]   raddr1,
  input [2:0]   raddr2,
  input [2:0]   waddr,
  input [15:0]  wdata,
  input         clk_n,
  input         rst_n,
  input         wea,
  output [15:0] rdata1,
  output [15:0] rdata2
);

// 16 bits wide, 2^3 bits deep register file
// {$0,$A,$B,$C,$D,$E,$F,$G}
reg [15:0] registers [7:1];

// Reads are combinational
assign rdata1 = (raddr1 == 3'b000) ? 16'h0000 : registers[raddr1];
assign rdata2 = (raddr2 == 3'b000) ? 16'h0000 : registers[raddr2];

// Writes only happen when wea is high and rising edge of clock
always@(posedge clk_n or negedge rst_n) begin
  if(!rst_n) begin
    registers[3'h1] <= 16'b0;
    registers[3'h2] <= 16'b0;
    registers[3'h3] <= 16'b0;
    registers[3'h4] <= 16'b0;
    registers[3'h5] <= 16'b0;
    registers[3'h6] <= 16'b0;
    registers[3'h7] <= 16'b0;
  end else begin
    if(wea) begin
      if(waddr != 3'h0) begin
        registers[waddr] <= wdata;
      end
    end
  end
end

endmodule
